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mcm69d536 1 motorola fast sram 32k x 36 bit synchronous dual i/o, dual address sram the mcm69d536 is a 1mbit static random access memory, organized as 32k words of 36 bits. it features common data input and data output buffers and incorporates input and output registers onboard with high speed sram. the mcm69d536 allows the user to concurrently perform reads, writes, or passthrough cycles in combination on the two data ports. the two address ports (ax, ay) determine the read or write locations for their respective data ports (dqx, dqy). the synchronous design allows for precise cycle control with the use of an external single clock (k). all signal pins except output enables (gx , gy ) are registered on the rising edge of clock (k). the passthrough feature allows data to be passed from one port to the other, in either direction. the ptx input must be asserted to pass data from port x to port y. the pty will likewise pass data from port y to port x. a passthrough operation takes precedence over a read operation. for the case when ax and ay are the same, certain protocols are followed. if both ports are read, the reads occur normally. if one port is written and the other is read, the read from the array will occur before the data is written. if both ports are written, only the data on dqy will be written to the array. ? single 3.3 v 5% power supply ? fast access times: 6/8 ns max ? throughput of 2.98 gigabits/second ? single clock operation ? address, data input, e1 , e2, ptx , pty , wx , wy , and data output registers onchip ? 83 mhz maximum clock frequency ? selftimed write ? two bidirectional data buses ? can be configured as separate i/o ? passthrough feature ? asynchronous output enables (gx , gy ) ? lvttl compatible i/o ? concurrent reads and writes ? 176pin tqfp package suggested applications e atm e ethernet switches e routers e cell/frame buffers e sna switches e shared memory product family configurations part number dual address single address dual i/o separate i/o configuration v dd mcm69d536 note 1 note 2 32k x 36 3.3 v mcm69d618 note 1 note 2 64k x 18 3.3 v mcm67q709a 128k x 9 5.0 v mcm67q909 512k x 9 5.0 v notes: 1. tie ax and ay address ports together for the part to function as a single address part. 2. tie gx high for dqx to be inputs and tie wy high and gy low for dqy to be outputs. order this document by mcm69d536/d semiconductor technical data mcm69d536 tq package 176 lead tqfp case 110101 rev 4 1/16/98 ? motorola, inc. 1998
mcm69d536 2 motorola fast sram ax e1 wx block diagram ptx address register 32k x 36 array gx e2 address register 15 write x register ptx register passthrough dqx ay write driver sense amps sense amps write driver write y register wy pty register pty data in register output register output register data in register enable reg 1 gy dqy 15 enable reg 2 k k
mcm69d536 3 motorola fast sram pin assignment dqx20 51 52 48 49 50 56 57 53 54 55 59 60 58 45 46 47 64 63 62 61 v dd v ss v dd v ss dqy20 dqx21 dqy21 dqx22 dqy22 dqx23 dqy23 dqx24 dqx35 dqy34 dqx34 v ssi dqy35 dqx25 dqy24 v ss dqy28 dqx28 dqy25 v dd v ss dqy27 dqx27 v ssi 10 9 12 11 15 14 13 17 16 20 19 18 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 8 v dd dqx26 dqy26 v dd v ss dqy29 71 72 69 68 70 76 77 73 74 75 79 80 78 65 66 67 84 83 82 81 dqy0 nc nc nc dqx0 nc 88 87 86 85 dqy1 dqx1 dqy30 v dd v ss v dd v ss dqx30 dqy31 dqx31 dqy32 dqx32 dqy33 dqx33 v ssi dqx29 40 39 42 41 44 43 37 36 35 34 33 32 31 38 dqx2 v dd v ss v dd v ss dqy2 dqx3 dqy3 dqx4 dqy4 dqx5 dqy5 dqx6 dqx17 dqy16 dqx16 nc nc dqy17 dqx7 dqy6 v ss dqy10 dqx10 dqy7 v dd v ss dqy9 dqx9 v ssi 98 97 100 99 103 102 101 105 104 108 107 106 109 110 111 112 113 114 115 116 117 118 95 94 93 92 91 89 90 96 v dd dqx8 dqy8 v dd v ss dqy11 e2 gx pty wx wy e1 ptx nc k nc nc nc nc gy nc dqy18 ax7 ay6 ax6 dqx18 ay7 dqy19 dqx19 dqy12 v dd v ss v dd v ss dqx12 dqy13 dqx13 dqy14 dqx14 dqy15 dqx15 v ssi dqx11 128 127 130 129 132 131 125 124 123 122 121 120 119 126 170 175 174 173 172 168 169 165 164 167 176 171 166 158 157 162 161 160 159 163 150 155 154 153 152 148 149 145 144 147 156 151 138 137 142 141 140 139 143 134 133 136 135 146 v ssi v ss v dd v ssi ay5 ax5 ay4 ax4 ay3 ax3 ay2 ax2 ay1 ax1 ay0 ax0 v ss v dd ax10 ay10 ax11 ay11 ax12 ay12 ax13 ay13 ax14 ay14 v dd v ss v ssi v ssi v dd v ss ax9 ay9 ax8 ay8 v dd v ss nc nc v ssi v ss v ssi v dd
mcm69d536 4 motorola fast sram pin descriptions pin locations symbol type description 65, 63, 61, 59, 57, 55, 169, 167, 145, 143, 68, 70, 72, 74, 76 ax0 ax14 input address port x. never allow floating addresses for inputs ax0 ax14. a pullup resistor is needed. 64, 62, 60, 58, 56, 54, 168, 166, 144, 142, 69, 71, 73, 75, 77 ay0 ay14 input address port y. never allow floating addresses for inputs ay0 ay14. a pullup resistor is needed. 82, 86, 90, 94, 96, 100, 102, 106, 108, 113. 115, 119, 121, 125, 127, 131, 135, 139, 170, 174, 2, 6, 8, 12, 14, 18, 20, 25, 27, 31, 33, 37, 39, 43, 47, 51 dqx0 dqx35 i/o data input/output port x. 83, 87, 91, 95, 97, 101, 103, 107, 109, 112, 114, 118, 120, 124, 126, 130, 134, 138, 171, 175, 3, 7, 9, 13, 15, 19, 21, 24, 26, 30, 32, 36, 38, 42, 46, 50 dqy0 dqy35 i/o data input/output port y. 150 e1 input synchronous chip enable: active low. 151 e2 input synchronous chip enable: active high. 152 gx input asynchronous output enable port x input: low e enables output buffers (dqxx pins). high e dqxx pins are high impedance. 153 gy input asynchronous output enable port y input: low e enables output buffers (dqyx pins). high e dqyx pins are high impedance. 156 k input clock: this signal registers the address, data in, and all control signals except g . 146 ptx input passthrough port x. 147 pty input passthrough port y. 148 wx input synchronous write enable port x. 149 wy input synchronous write enable port y. 4, 10, 16, 22, 28, 34, 40, 49, 67, 84, 92, 98, 104, 110, 116, 122, 128, 137, 155, 172 v dd supply + 3.3 v power supply. 5, 11, 17, 23, 29, 35, 41, 48, 66, 85, 93, 99, 105, 111, 117, 123. 129, 136, 154, 173 v ss supply ground. 1, 44, 45, 52, 53, 88, 89, 132, 133, 165, 176 v ssi input bonded to die flag. no chip current flows through these pins. 78 81, 140, 141, 157 164 nc e no connection: there is no connection to the chip.
mcm69d536 5 motorola fast sram truth table (see notes 1 through 5) oinb input at t n clock operation number e1 e2 wx wy ptx pty operation 1 h x x x x x deselected 2 x l x x x x deselected 3 l h 0 x x x write x port 4 l h x 0 x x write y port 5 l h x x 0 x passthrough x to y 6 l h x x x 0 passthrough y to x 7 l h 1 x 1 1 read x 8 l h x 1 1 1 read y notes: 1. gx /gy must be controlled to avoid bus contention issues during write and passthrough cycles. 2. operation numbers 3 6 can be used in any combination. 3. operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined. 4. operation number 5 can not be combined with operation number 7 or 8 because passthrough takes precedence over a read operation. 5. operation number 6 can not be combined with operation number 7 or 8 because passthrough takes precedence over a read operation. k address & control valid t n t n + 1 valid data input d valid data output q pipelined read access passthrough absolute maximum ratings (see note) rating symbol value unit power supply voltage v dd 0.5 to + 4.6 v voltage relative to v ss for any pin except v dd v in , v out 0.5 to v dd + 0.5 v output current i out 20 ma power dissipation p d tbd w temperature under bias t bias 10 to + 85 c operating temperature t a 0 to + 70 c storage temperature e plastic t stg 55 to + 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. this is a synchronous device. all synchro- nous inputs must meet specified setup and hold times with stable logic levels for all rising edges of clock (k) while the device is selected. this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to these highimpedance circuits.
mcm69d536 6 motorola fast sram package thermal characteristics (see note 1) rating symbol tqfp unit notes junction to ambient (@ 200 lfm) singlelayer board fourlayer board r q ja 40 35 c/w 2 junction to board (bottom) r q jb 23 c/w 3 junction to case (top) r q jc 9 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface via the cold plate method (mil spec883 method 1012.1). dc operating conditions and characteristics (v dd = 3.3 v 5%, t a = 0 to + 70 c, unless otherwise noted) recommended operating conditions and supply currents parameter symbol min max unit supply voltage (operating voltage range) v dd 3.135 3.465 v input high voltage v ih 2.0 v dd + 0.5** v input low voltage v il 0.5* 0.8 v input leakage current (all inputs, v in = 0 to v dd ) i lkg(i) e 1.0 m a output leakage current (e = v ih , v out = 0 to v dd ) i lkg(o) e 1.0 m a ac supply current (i out = 0 ma) (v dd = max, f = f max ) mcm69d5366 ns mcm69d5368 ns i dda e e 300 300 ma cmos standby supply current (deselected, clock (k) mcm69d5366 ns cycle time t khkh , all inputs toggling at cmos levels mcm69d5368 ns v in v ss + 0.2 v or v dd 0.2 v) i sb1 e e 100 100 ma output low voltage (i ol = + 8.0 ma) v ol e 0.4 v output high voltage (i oh = 4.0 ma) v oh 2.4 v dd v *v il 1.5 v for t t khkh /2. ** v ih v dd + 1.0 v for t t khkh /2. capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 0 to 70 c, periodically sampled rather than 100% tested) parameter symbol max unit address and data input capacitance c in 6 pf control pin input capacitance c in 6 pf output capacitance c out 8 pf
mcm69d536 7 motorola fast sram ac operating conditions and characteristics (v dd = 3.3 v 5%, t a = 0 to + 70 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load figure 1 unless otherwise noted . . . . . . . . . . . . . . . . . . read/write cycle timing (see notes 1, 2, and 3) mcm69d5366 mcm69d5368 parameter symbol min max min max unit notes cycle time t khkh 12 e 15 e ns 1 clock access time t khqv e 6 e 8 ns clock low pulse width t klkh 4 e 6 e ns clock high pulse width t khkl 4 e 6 e ns clock high to data output active t khqx1 0 e 0 e ns clock high to data output invalid t khqx2 2 e 2 e ns clock high to data output highz t khqz e 5 e 5 ns 2 output enable low to data output valid t glqv e 6 e 8 ns output enable low to data output lowz t glqx 0 e 0 e ns output enable high to data output highz t ghqz e 5 e 8 ns 2 setup times: awr0 awr14 ard0 ard14 w pt e1 , e2 d0 d35 t avkh t avkh t wvkh t ptvkh t evkh t dvkh 2.5 e 3 e ns 3 hold times: awr0 awr14 ard0 ard14 w pt e1 , e2 d0 d35 t khax t khax t khwx t khptx t khex t khdx 0.5 e 1 e ns 3 3 3 3 3 3, 4 notes: 1. all read and write cycles are referenced from k. 2. this parameter is sampled and not 100% tested. 3. this is a synchronous device. all synchronous inputs must meet the specified setup and hold times with stable logic levels for all rising edges of clock (k) while the device is selected. 4. t khdx minimum for port y only extends to 4.0 ns only for the special case when the y and xaddress are identical on the same rising clock edge. output z 0 = 50 w r l = 50 w v l = 1.5 v figure 1. ac test load
mcm69d536 8 motorola fast sram 1 k ax e t khkh t klkh t khkl 2 3 4 5 6 7 8 9 gx dqx t glqv t ghqz t khqv t khqx1 q(1) q(2) q(3) q(5) q(6) 12 ay 13 14 15 16 6 7 19 20 gy dqy t khqz q(12) q(13) q(14) q(16) q(6) q(7) q(7) t glqx t evkh t khex t khqv port x port y note: e low = e1 low and e2 high. e high = e1 high or e2 low. t avkh t khax read cycle timing from both ports (wx , wy , ptx , pty high)
mcm69d536 9 motorola fast sram k ax e t khkh t klkh t khkl gx dqx ay gy d(2) d(3) d(4) d(5) d(6) d(8) d(9) t khwx port x wx port y wy dqy d(14) d(15) d(19) d(18) t wvkh t khdx t dvkh note: e low = e1 low and e2 high. e high = e1 high or e2 low. port y takes precedence over port x when ax = ay and writing both ports. write cycle timing to both ports (ptx , pty high) 1 2 3 4 5 6 7 8 9 12 13 14 15 5 6 18 19 20
mcm69d536 10 motorola fast sram t khptx k ax e t khkh t klkh t khkl gx dqx ay gy d(2) d(3) d(x) d(y) d(6) t khqv port x wx port y wy dqy t khqx2 t khdx t dvkh e low = e1 low and e2 high. e high = e1 high or e2 low. note: the timing diagram is valid for the opposite case as well, i.e., writing to port y and passing through to port x. ptx pty d(3) d(x) d(y) d(17) t khqz t ptvkh write to port x and passthrough to port y (see note) 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20
mcm69d536 11 motorola fast sram gy dqy d(pqr) d(xyz) q(pqr) d(jkl) q(jkl) port y takes precedence over port x when ax = ay and writing both ports. 1 k ax t khkh t klkh t khkl 2 1 2 3 gx dqx d(abc) d(def) port x wx read read read read read read q(xyz) q(jkl) q(pqr) try to write try to write combination read/write with same address on each port ay wy 1 2 1 2 3 write write read read read write read read port y ptx = pty = high. d(value) = value is the input to the data port. q(value) = value is the output from the data port.
mcm69d536 12 motorola fast sram motorola memory prefix part number package (tq = tqfp) full part numbers e mcm69d536tq6 mcm69d536tq8 mcm69d536tq6r mcm69d536tq8r shipping method (r = tape and reel, blank = rails) speed (6 = 6ns, 8 = 8 ns) mcm 69d536 xx xx x ordering information (order by full part number)
mcm69d536 13 motorola fast sram tqfp package 176 lead case 110101 package dimensions c l m b notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the the lead exits the plastic body at the bottom of the parting line. 4. datums l, m, and n to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane t. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do inlcude mold mismatch and are determined at datum plane h. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.35 (0.014) minimum space between protrusion and adjacent lead 0.07 (0.003). pin 1 1 dim min max millimeters a 24.00 bsc a1 12.00 bsc b 24.00 bsc b1 12.00 bsc c 1.60 c1 0.05 c2 1.35 1.45 d 0.17 0.23 e 0.45 0.75 f 0.17 0.27 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.10 0.20 s 26.00 bsc s1 13.00 bsc u 0.09 0.16 v 26.00 bsc v1 13.00 bsc w 0.20 ref z 1,00 ref 0 7 1 0 2 12 ref ??? ??? ??? ab ab g p x=l, m, n x view y c l rotated 90 clockwise ident seating plane gage plane a a1 c2 w 1 z k e view aa 0.25 r1 2x r c1 s 0.05 m 0.08 t base plating metal f j u view y 4x 44 tips d s lm s n section abab c l 4x 3x 176 133 132 45 88 44 89 n l lm n t 0.20 lm n h 0.20 s s1 v1 b1 c view aa v h t 2 4x t 0.08
mcm69d536 14 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 141, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 nishi-gotanda, shagawa-ku, tokyo, japan. 03-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & c anada only 1-800-774-1848 51 ting kok road, tai po, n.t., hong kong. 852-26629298 http ://sps.motorola.com /mfax / home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm69d536/d ?

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